In recent years, the number of processor cores (hereinafter, described as “cores”) as arithmetic processing units integrated on a chip of a central processing unit (CPU) is increasing in order to improve the performance of the CPU and suppress an increase in the power consumption due to a high frequency clock. Furthermore, as a technology for connecting the cores on the same chip, a ring network and a mesh network for example are known.
Patent Document 1: Japanese Laid-open Patent Publication No. 2005-174289
Patent Document 2: Japanese National Publication of International Patent Application No. 2004-538548
Patent Document 3: Japanese Laid-open Patent Publication No. 2005-339348
However, in the related technology as described above, it is impossible to improve the performance with an increase in the number of cores.
For example, when the number of cores increases, it is desirable to increase the bisection bandwidth (Bisection Bandwidth). However, if the cores are connected in a single ring, a communication distance between the cores increases, so that the bisection bandwidth is not increased even when the number of cores increases.
Furthermore, in the mesh network in which a storage area is divided into banks, when a core accesses a storage area other than the storage area managed by itself, the core accesses a cache memory of an external core. Therefore, when the core frequently accesses the cache memory of the external core, latency is increased. Moreover, if a number of cores access storage areas other than the storage areas managed by themselves, load on the communication network between the cores increases. The increase in the latency or the load on the communication network between the cores occurs not only in the mesh network but also in any structure in which a storage area is divided into banks.